UPD78F0411GA-GAM-AX Datasheet, PDF (459/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 19 STANDBY FUNCTION
19.1.2 Registers controlling standby function
The standby function is controlled by the following two registers.
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
(1) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1
clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock,
the X1 clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of
MOC register) = 1 clear OSTC to 00H.
Figure 19-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H After reset: 00H R
Symbol
7
6
5
OSTC
0
0
0
4
MOST11
3
MOST13
2
MOST14
1
MOST15
0
MOST16
MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status
fX = 10 MHz
1
0
0
0
0
2¹¹/fX min.
204.8 μs min.
1
1
0
0
0
2¹³/fX min.
819.2 μs min.
1
1
1
0
0
2¹⁴/fX min.
1.64 ms min.
1
1
1
1
0
2¹⁵/fX min.
3.27 ms min.
1
1
1
1
1
2¹⁶/fX min.
6.55 ms min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
2. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
3. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark fX: X1 clock oscillation frequency
User’s Manual U18698EJ1V0UD
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