UPD78F0411GA-GAM-AX Datasheet, PDF (500/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 22 LOW-VOLTAGE DETECTOR
(2) When detecting level of input voltage from external input pin (EXLVI)
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from
external input pin (EXLVI)).
<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<4> Use software to wait for an operation stabilization time (10 μs (MAX.)).
<5> Confirm that “input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI = 1.21 V (TYP.)”
when detecting the falling edge of EXLVI, or “input voltage from external input pin (EXLVI) < detection
voltage (VEXLVI = 1.21 V (TYP.)” when detecting the rising edge of EXLVI, at bit 0 (LVIF) of LVIM.
<6> Clear the interrupt request flag of LVI (LVIIF) to 0.
<7> Release the interrupt mask flag of LVI (LVIMK).
<8> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value).
<9> Execute the EI instruction (when vector interrupts are used).
Figure 22-8 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <8> above.
Caution Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
• When using 1-bit memory manipulation instruction:
Clear LVION to 0.
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User’s Manual U18698EJ1V0UD