UPD78F0411GA-GAM-AX Datasheet, PDF (172/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(2) Operation in clear & start mode entered by TI000 pin valid edge input
(CR000: compare register, CR010: capture register)
Figure 6-25. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Compare Register, CR010: Capture Register)
TI000 pin
Count clock
Edge
detector
Operable bits
TMC003, TMC002
Clear
Timer counter
(TM00)
Match signal
Compare register
(CR000)
Output
controller
Interrupt signal
(INTTM000)
TO00
output
TO00 pin
Capture signal
Capture register
(CR010)
Interrupt signal
(INTTM010)
Figure 6-26. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Compare Register, CR010: Capture Register) (1/2)
(a) TOC00 = 13H, PRM00 = 10H, CRC00, = 04H, TMC00 = 08H, CR000 = 0001H
TM00 register
0000H
Operable bits ₀₀
(TMC003, TMC002)
Capture & count clear input
(TI000 pin input)
Compare register
(CR000)
Compare match interrupt
(INTTM000)
Capture register
(CR010)
Capture interrupt
(INTTM010)
M
N
S
10
0001H
0000H
M
N
P
S
Q
P
Q
TO00 output
This is an application example where the TO00 output level is inverted when the count value has been captured
& cleared.
The count value is captured to CR010 and TM00 is cleared (to 0000H) when the valid edge of the TI000 pin is
detected. When the count value of TM00 is 0001H, a compare match interrupt signal (INTTM000) is generated,
and the TO00 output level is inverted.
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User’s Manual U18698EJ1V0UD