UPD78F0411GA-GAM-AX Datasheet, PDF (76/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 3 CPU ARCHITECTURE
3.4.8 Based indexed addressing
[Function]
The B or C register contents specified in an instruction word are added to the contents of the base register, that
is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the
sum is used to address the memory. Addition is performed by expanding the B or C register contents as a
positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all of the
memory spaces.
[Operand format]
Identifier
−
[HL + B], [HL + C]
Description
[Description example]
MOV A, [HL +B]; when selecting B register
Operation code
10101011
[Illustration]
16
87
HL
H
+
7
0
L
0
B
The contents of the memory
addressed are transferred.
7
A
7
Memory
0
0
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User’s Manual U18698EJ1V0UD