UPD78F0411GA-GAM-AX Datasheet, PDF (283/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 10 WATCHDOG TIMER
10.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Table 10-1. Configuration of Watchdog Timer
Item
Control register
Configuration
Watchdog timer enable register (WDTE)
How the counter operation is controlled, overflow time, and window open period are set by the option byte.
Table 10-2. Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer
Option Byte (0080H)
Window open period
Bits 6 and 5 (WINDOW1, WINDOW0)
Controlling counter operation of watchdog timer
Bit 4 (WDTON)
Overflow time of watchdog timer
Bits 3 to 1 (WDCS2 to WDCS0)
Remark For the option byte, see CHAPTER 23 OPTION BYTE.
Figure 10-1. Block Diagram of Watchdog Timer
CPU access signal
CPU access
error detector
WDCS2 to WDCS0 of
option byte (0080H)
fRL/2
Clock
input
controller
17-bit
counter
2¹⁰/fRL to
2¹⁷/fRL
Overflow
signal
Selector
WINDOW1 and WINDOW0
of option byte (0080H)
Count clear
signal
Clear, reset control
Window size
determination
signal
Reset
output
controller
Internal reset signal
WDTON of option
byte (0080H)
Watchdog timer enable
register (WDTE)
Internal bus
User’s Manual U18698EJ1V0UD
281