UPD78F0411GA-GAM-AX Datasheet, PDF (536/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 26 INSTRUCTION SET
Instruction
Mnemonic
Group
Operands
16-bit
operation
Multiply/
divide
Increment/
decrement
ADDW
SUBW
CMPW
MULU
DIVUW
INC
AX, #word
AX, #word
AX, #word
X
C
r
saddr
DEC
INCW
r
saddr
rp
DECW
rp
Rotate
ROR
A, 1
ROL
A, 1
RORC
A, 1
ROLC
A, 1
ROR4
[HL]
ROL4
[HL]
BCD
ADJBA
adjustment _ADJBS
Bit
MOV1
manipulate
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit, CY
sfr.bit, CY
A.bit, CY
PSW.bit, CY
[HL].bit, CY
Bytes
Clocks
Note 1 Note 2
Operation
3
6
− AX, CY ← AX + word
3
6
− AX, CY ← AX − word
3
6
− AX − word
2 16
− AX ← A × X
2 25
− AX (Quotient), C (Remainder) ← AX ÷ C
1
2
− r←r+1
2
4
6 (saddr) ← (saddr) + 1
1
2
− r←r−1
2
4
6 (saddr) ← (saddr) − 1
1
4
− rp ← rp + 1
1
4
− rp ← rp − 1
1
2
− (CY, A7 ← A0, Am − 1 ← Am) × 1 time
1
2
− (CY, A0 ← A7, Am + 1 ← Am) × 1 time
1
2
− (CY ← A0, A7 ← CY, Am − 1 ← Am) × 1 time
1
2
− (CY ← A7, A0 ← CY, Am + 1 ← Am) × 1 time
2
10
12 A3 − 0 ← (HL)3 − 0, (HL)7 − 4 ← A3 − 0,
(HL)3 − 0 ← (HL)7 − 4
2
10
12 A3 − 0 ← (HL)7 − 4, (HL)3 − 0 ← A3 − 0,
(HL)7 − 4 ← (HL)3 − 0
2
4
− Decimal Adjust Accumulator after Addition
2
4
− Decimal Adjust Accumulator after Subtract
3
6
7 CY ← (saddr.bit)
3
−
7 CY ← sfr.bit
2
4
− CY ← A.bit
3
−
7 CY ← PSW.bit
2
6
7 CY ← (HL).bit
3
6
8 (saddr.bit) ← CY
3
−
8 sfr.bit ← CY
2
4
− A.bit ← CY
3
−
8 PSW.bit ← CY
2
6
8 (HL).bit ← CY
Flag
Z AC CY
×××
×××
×××
××
××
××
××
×
×
×
×
×××
×××
×
×
×
×
×
××
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
534
User’s Manual U18698EJ1V0UD