UPD78F0411GA-GAM-AX Datasheet, PDF (212/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-56. Operation Flowchart of External 24-bit Event Counter
Set TMH2 to PWM mode
Note
Set TM52 to external event counter
Set TM00 to interval timer
Starts TM00 count operation
Starts TM52 count operation
Set in this order
Starts TMH2 count operation
Note
Generates INTTMH2?
Read TM00 counter value
Read TM52 counter value
TMC003 = 0, TMC002 = 0
TCE52 = 0
Clear TM00 counter value
Clear TM52 counter value
Perform these steps during
low-level output of TOH2
These operations must be restarted
since the counter is cleared when
timer operation is stopped.
Starts TM00 count operation
Starts TM52 count operation
Note This setting is not required if input enable for the TI52 pin is not controlled.
6.4.10 Cautions for external 24-bit event counter
(1) 8-bit timer counter H2 output signal
The output level control (default value) of 8-bit timer H2 which is used to control input enable for the TI52 pin,
must be set to high level (TOLEV2 = 1). Consequently, an interrupt request signal (INTTMH2) is generated while
the input enable signal to the TI52 pin is disabled (TMH2 output: low level), and the TM52 and TM00 count values
(= external event count value in input enable period) can be read via servicing of this interrupt.
Note with caution that the input enable signal to the TI52 pin is at high level (enable status) until the TMH2 and
CMP02 register values match, after 8-bit timer H2 operation has been enabled (TMHE2 = 1) via this setting
(TOLEV2 = 1).
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User’s Manual U18698EJ1V0UD