UPD78F0411GA-GAM-AX Datasheet, PDF (75/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 3 CPU ARCHITECTURE
3.4.7 Based addressing
[Function]
8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in
the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address
the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from
the 16th bit is ignored. This addressing can be carried out for all of the memory spaces.
[Operand format]
Identifier
−
[HL + byte]
Description
[Description example]
MOV A, [HL + 10H]; when setting byte to 10H
Operation code
10101110
[Illustration]
16
HL
H
The contents of the memory
addressed are transferred.
7
A
00010000
87
7
0
L
Memory
0
0
+10H
User’s Manual U18698EJ1V0UD
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