UPD78F0411GA-GAM-AX Datasheet, PDF (475/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 20 RESET FUNCTION
Figure 20-4. Timing of Reset in STOP Mode by RESET Input
Internal high-speed
oscillation clock
High-speed system clock
(when X1 oscillation is selected)
CPU clock
RESET
STOP instruction execution
Wait for oscillation
accuracy stabilization
(86 to 361 μs)
Starting X1 oscillation is specified by software.
Normal
operation
Stop status
Reset period
(oscillation stop) (oscillation stop)
Reset
processing
(11 to 47 μs)
Normal operation
(internal high-speed oscillation clock)
Internal reset signal
Port pin
Delay
Delay
(5 μs (TYP.))
Hi-Z
Remark For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 21 POWER-
ON-CLEAR CIRCUIT and CHAPTER 22 LOW-VOLTAGE DETECTOR.
User’s Manual U18698EJ1V0UD
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