UPD78F0411GA-GAM-AX Datasheet, PDF (385/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 15 LCD CONTROLLER/DRIVER
(3) LCD clock control register (LCDC0)
LCDC0 specifies the LCD source clock and LCD clock.
The frame frequency is determined according to the LCD clock and the number of time slices.
LCDC0 is set using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets LCDC0 to 00H.
Figure 15-4. Format of LCD Clock Control Register
Address: FFB2H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
LCDC0
0
LCDC6
LCDC5
LCDC4
0
LCDC2
LCDC1
LCDC0
LCDC6
LCDC5
0
0
0
0
0
1
0
1
1
0
Other than above
LCDC4
0
1
0
1
0
fXT (32.768 kHz)
fPRS/2⁶
fPRS/2⁷
fPRS/2⁸
fRL/2³
Setting prohibited
LCD source clock (fLCD) selection
LCDC2
LCDC1
0
0
0
0
0
1
0
1
1
0
1
0
Other than above
LCDC0
0
1
0
1
0
1
fLCD/2⁴
fLCD/2⁵
fLCD/2⁶
fLCD/2⁷
fLCD/2⁸
fLCD/2⁹
Setting prohibited
LCD clock (LCDCL) selection
Caution Bits 3 and 7 must be set to 0.
Remarks 1.
2.
3.
fXT:
fPRS:
fRL:
XT1 clock oscillation frequency
Peripheral hardware clock frequency
Internal low-speed oscillation clock frequency
User’s Manual U18698EJ1V0UD
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