UPD78F0411GA-GAM-AX Datasheet, PDF (251/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 8 8-BIT TIMERS H0, H1, AND H2
8.4.2 Operation as PWM output
In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
The 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n
register during timer operation is prohibited.
The 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n
register during timer operation is possible.
The operation in PWM output mode is as follows.
PWM output (TOHn output) outputs an active level and 8-bit timer counter Hn is cleared to 0 when 8-bit timer
counter Hn and the CMP0n register match after the timer count is started. PWM output (TOHn output) outputs an
inactive level when 8-bit timer counter Hn and the CMP1n register match.
The timer output of TMH2 (PWM output) can only be used as an external event input enable signal of TM52. Note,
no pins for external output are available.
Setting
<1> Set each register.
Figure 8-13. Register Setting in PWM Output Mode
(i) Setting timer H mode register n (TMHMDn)
TMHEn
TMHMDn
0
CKSn2 CKSn1
0/1
0/1
CKSn0 TMMDn1 TMMDn0 TOLEVn TOENn
0/1
1
0
0/1
1
Timer output enabled
Default setting of timer output level
PWM output mode selection
Count clock (fCNT) selection
Count operation stopped
(ii) Setting CMP0n register
• Compare value (N): Cycle setting
(iii) Setting CMP1n register
• Compare value (M): Duty setting
Remarks 1. n = 0 to 2, however, TOH0 and TOH1 only for TOHn
2. 00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
<2> The count operation starts when TMHEn = 1.
<3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled.
When the values of the 8-bit timer counter Hn and the CMP0n register match, the 8-bit timer counter Hn is
cleared, an interrupt request signal (INTTMHn) is generated, an active level is output. At the same time, the
compare register to be compared with the 8-bit timer counter Hn is changed from the CMP0n register to the
CMP1n register.
User’s Manual U18698EJ1V0UD
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