UPD78F0411GA-GAM-AX Datasheet, PDF (231/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52
7.4 Operations of 8-Bit Timer/Event Counters 50, 51, and 52
7.4.1 Operation as interval timer
8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals
of the count value preset to 8-bit timer compare register 5n (CR5n).
When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the
TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n
(TCL5n).
Setting
<1> Set the registers.
• TCL5n: Select the count clock.
• CR5n: Compare value
• TMC5n: Stop the count operation.
(TMC50 = 0000×××0B, TMC51 = TMC52 = 00000000B × = Don’t care)
<2> After TCE5n = 1 is set, the count operation starts.
<3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).
<4> INTTM5n is generated repeatedly at the same interval.
Set TCE5n to 0 to stop the count operation.
Caution Do not write other values to CR5n during operation.
Remarks 1. For how to enable the INTTM5n signal interrupt, see CHAPTER 17 INTERRUPT FUNCTIONS.
2. n = 0 to 2
Figure 7-14. Interval Timer Operation Timing (1/2)
t
Count clock
TM5n count value 00H 01H
Count start
CR5n
N
TCE5n
INTTM5n
(a) Basic operation
N 00H 01H
Clear
N
N 00H 01H
N
Clear
N
N
Interrupt acknowledged
Interval time
Interrupt acknowledged
Interval time
Remark
Interval time = (N + 1) × t
N = 01H to FFH
n = 0 to 2
User’s Manual U18698EJ1V0UD
229