UPD78F0411GA-GAM-AX Datasheet, PDF (134/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATOR
(1) Example of setting procedure when oscillating the XT1 clock
<1> Setting XT1 and XT2 pins and selecting operation mode (PCC and OSCCTL registers)
When OSCSELS is set as any of the following, the mode is switched from port mode to XT1 oscillation
mode.
OSCSELS Operation Mode of Subsystem
Clock Pin
P123/XT1 Pin
P124/XT2 Pin
1
XT1 oscillation mode
Crystal/ceramic resonator connection
<2> Waiting for the stabilization of the subsystem clock oscillation
Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function.
Caution Do not change the value of OSCSELS while the subsystem clock is operating.
(2) Example of setting procedure when using the subsystem clock as the CPU clock
<1> Setting subsystem clock oscillation^Note
(See 5.6.3 (1) Example of setting procedure when oscillating the XT1 clock)
Note The setting of <1> is not necessary when while the subsystem clock is operating.
<2> Switching the CPU clock (PCC register)
When CSS is set to 1, the subsystem clock is supplied to the CPU.
CSS
1
PCC2
PCC1
PCC0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
Other than above
fSUB/2
CPU Clock (fCPU) Selection
Setting prohibited
(3) Example of setting procedure when stopping the subsystem clock
<1> Confirming the CPU clock status (PCC and MCM registers)
Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock.
When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal
high-speed oscillation clock or high-speed system clock.
CLS
MCS
CPU Clock Status
0
0
Internal high-speed oscillation clock
0
1
High-speed system clock
1
×
Subsystem clock
<2> Stopping the subsystem clock (OSCCTL register)
When OSCSELS is cleared to 0, XT1 oscillation is stopped.
Cautions 1. Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the
peripheral hardware if it is operating on the subsystem clock.
2. The subsystem clock oscillation cannot be stopped using the STOP instruction.
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User’s Manual U18698EJ1V0UD