UPD78F0411GA-GAM-AX Datasheet, PDF (383/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 15 LCD CONTROLLER/DRIVER
(2) LCD display mode register (LCDM)
LCDM specifies whether to enable display operation. It also specifies whether to enable segment
pin/common pin output, gate booster circuit control, and the display mode.
LCDM is set using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets LCDM to 00H.
Figure 15-3. Format of LCD Display Mode Register
Address: FFB1H After reset: 00H R/W
Symbol
<7>
<6>
5
LCDM LCDON
SCOC
0
<4>
VAON
3
2
1
0
0
LCDM2
LCDM1
LCDM0
LCDON
0
1
LCD display enable/disable
Display off (all segment outputs are deselected.)
Display on
SCOC
0
1
Segment pin/common pin output control^{Note 1}
Output ground level to segment/common pin
Output deselect level to segment pin and LCD waveform to common pin
VAON
0
1
No gate voltage boosting
Gate voltage boosting
Gate booster circuit control^{Notes 1, 2}
LCDM2
LCDM1
1
1
0
0
0
0
0
1
0
1
1
0
Other than above
LCDM0
1
0
1
0
1
0
LCD controller/driver display mode selection
Resistance division method
Number of time slices
8
Bias mode
1/4 ^{Note 3}
4
1/3
3
1/3
2
1/2
3
1/2
Static
Setting prohibited
(Note and Caution are listed on the next page.)
User’s Manual U18698EJ1V0UD
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