UPD78F0411GA-GAM-AX Datasheet, PDF (246/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 8 8-BIT TIMERS H0, H1, AND H2
Figure 8-8. Format of 8-Bit Timer H Mode Register 2 (TMHMD2)
Address: FF42H After reset: 00H R/W
<7>
6
5
4
3
2
<1>
<0>
TMHMD2 TMHE2 CKS22 CKS21 CKS20 TMMD21 TMMD20 TOLEV2 TOEN2
TMHE2
Timer operation enable
0 Stops timer count operation (counter is cleared to 0)
1 Enables timer count operation (count operation started by inputting clock)
CKS22 CKS21 CKS20
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
Other than above
f ^{Note 2}
PRS
fPRS/2
fPRS/2²
fPRS/2⁴
fPRS/2⁶
fPRS/2¹⁰
fPRS/2¹²
Count clock selection^{Note 1}
fPRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
2 MHz 5 MHz 10 MHz
1 MHz 2.5 MHz 5 MHz
500 kHz 1.25 MHz 2.5 MHz
125 kHz 312.5 kHz 625 kHz
31.25 kHz 78.13 kHz 156.25 kHz
1.95 kHz 4.88 kHz 9.77 kHz
0.49 kHz 1.22 kHz 2.44 kHz
Setting prohibited
TMMD21 TMMD20
Timer operation mode
0
0 Interval timer mode
1
0 Input enable width adjust mode for pins (PWM mode)
Other than above Setting prohibited
TOLEV2
0 Low level
1 High level
Timer output level control (in default mode)
TOEN2
0 Disables output
1
Enables output^{Note 3}
Timer output control
Notes 1.
2.
3.
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
• VDD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• VDD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V ≤ VDD < 2.7 V, the setting of CKS22 = CKS21 = CKS20 = 0 (count clock: fPRS) is
prohibited.
The timer output of TMH2 can only be used as an external event input enable signal of TM52. No pins
for external output are available.
Caution When TMHE2 = 1, setting the other bits of TMHMD2 is prohibited.
Remark fPRS: Peripheral hardware clock frequency
244
User’s Manual U18698EJ1V0UD