UPD78F0411GA-GAM-AX Datasheet, PDF (320/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 13 SERIAL INTERFACE UART0
Figure 13-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2)
PS01
0
0
1
1
PS00
0
1
0
1
Transmission operation
Does not output parity bit.
Outputs 0 parity.
Outputs odd parity.
Outputs even parity.
Reception operation
Reception without parity
Reception as 0 parity^Note
Judges as odd parity.
Judges as even parity.
CL0
Specifies character length of transmit/receive data
0
Character length of data = 7 bits
1
Character length of data = 8 bits
SL0
Specifies number of stop bits of transmit data
0
Number of stop bits = 1
1
Number of stop bits = 2
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial
interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur.
Cautions 1. To start the transmission, set POWER0 to 1 and then set TXE0 to 1. To stop the transmission,
clear TXE0 to 0, and then clear POWER0 to 0.
2. To start the reception, set POWER0 to 1 and then set RXE0 to 1. To stop the reception, clear
RXE0 to 0, and then clear POWER0 to 0.
3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If
POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started.
4. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable
transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after
TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock,
the transmission circuit or reception circuit may not be initialized.
5. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1.
6. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits.
7. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with
“number of stop bits = 1”, and therefore, is not affected by the set value of the SL0 bit.
8. Be sure to set bit 0 to 1.
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User’s Manual U18698EJ1V0UD