UPD78F0411GA-GAM-AX Datasheet, PDF (176/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-28. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Capture Register, CR010: Compare Register) (2/2)
(b) TOC00 = 13H, PRM00 = 10H, CRC00, = 03H, TMC00 = 0AH, CR010 = 0003H
TM00 register
0003H
0000H
Operable bits
(TMC003, TMC002)
00
Capture & count clear input
(TI000 pin input)
Capture register
(CR000)
Capture interrupt
(INTTM000) ^L
Compare register
(CR010)
Compare match interrupt
(INTTM010)
TO00 output
M
N
10
S
P
0000H
0003H
M
N
S
P
4
44
4
This is an application example where the width set to CR010 (4 clocks in this example) is to be output from the
TO00 pin when the count value has been captured & cleared.
TM00 is cleared (to 0000H) at the rising edge detection of the TI000 pin and captured to CR000 at the falling
edge detection of the TI000 pin. The TO00 output is inverted when TM00 is cleared (to 0000H) because the
rising edge of the TI000 pin has been detected or when the value of TM00 matches that of a compare register
(CR010).
When bit 1 (CRC001) of capture/compare control register 00 (CRC00) is 1, the count value of TM00 is captured
to CR000 in the phase reverse to that of the input signal of the TI000 pin, but the capture interrupt signal
(INTTM000) is not generated. However, the INTTM000 interrupt is generated when the valid edge of the TI010
pin is detected. Mask the INTTM000 signal when it is not used.
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User’s Manual U18698EJ1V0UD