UPD78F0411GA-GAM-AX Datasheet, PDF (160/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4 Operation of 16-Bit Timer/Event Counter 00
6.4.1 Interval timer operation
If bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register (TMC00) are set to 11 (clear & start
mode entered upon a match between TM00 and CR000), the count operation is started in synchronization with the
count clock.
When the value of TM00 later matches the value of CR000, TM00 is cleared to 0000H and a match interrupt signal
(INTTM000) is generated. This INTTM000 signal enables TM00 to operate as an interval timer.
Remarks 1. For the setting of I/O pins, see 6.3 (6) Port mode register 3 (PM3).
2. For how to enable the INTTM000 interrupt, see CHAPTER 17 INTERRUPT FUNCTIONS.
Figure 6-12. Block Diagram of Interval Timer Operation
Count clock
Operable bits
TMC003, TMC002
Clear
16-bit counter (TM00)
Match signal
CR000 register
INTTM000 signal
Figure 6-13. Basic Timing Example of Interval Timer Operation
TM00 register
N
N
N
N
0000H
Operable bits
(TMC003, TMC002) ⁰⁰
Compare register
(CR000)
Compare match interrupt
(INTTM000)
Interval
(N + 1)
11
N
Interval
(N + 1)
Interval
(N + 1)
Interval
(N + 1)
158
User’s Manual U18698EJ1V0UD