UPD78F0411GA-GAM-AX Datasheet, PDF (47/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 3 CPU ARCHITECTURE
Figure 3-4. Memory Map (μPD78F0403, 78F0413)
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
Special function registers
(SFR)
256 x 8 bits
General-purpose
registers
32 x 8 bits
Internal high-speed RAM
1024 x 8 bits
Data memory
space
FB00H
FAFFH
FA56H
FA55H
FA40H
FA3FH
Reserved
LCD display RAM
22 × 8 bits
Reserved
8000H
7FFFH
Program
memory space
0000H
Flash memory
32768 x 8 bits
7FFFH
108FH
108EH
1085H
1084H
1080H
107FH
1000H
0FFFH
0800H
07FFH
008FH
008EH
0085H
0084H
0080H
007FH
0040H
003FH
0000H
Program area
On-chip debug security
ID setting area^{Note 1}
10 × 8 bits
Option byte area^{Note 1}
5 × 8 bits
Program area
CALLF entry area
2048 × 8 bits
Program area
1905 × 8 bits
On-chip debug security
ID setting area^{Note 1}
10 × 8 bits
Option byte area^{Note 1}
5 × 8 bits
CALLT table area
64 × 8 bits
Vector table area
64 × 8 bits
1FFFH
Boot cluster 1
Boot cluster 0^{Note 2}
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security
IDs to 0085H to 008EH.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the
on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 24.7 Security
Setting).
Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.
7FFFH
7C00H
7BFFH
Block 1FH
07FFH
0400H
03FFH
0000H
Block 01H
Block 00H
1 KB
User’s Manual U18698EJ1V0UD
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