UPD78F0411GA-GAM-AX Datasheet, PDF (302/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only)
Figure 12-9. Format of A/D Port Configuration Register 0 (ADPC0)
Address: FF8FH After reset: 08H R/W
Symbol
7
6
5
4
3
2
1
0
ADPC0
0
0
0
0
0
ADPC02
ADPC01
ADPC00
ADPC02
ADPC01
ADPC00
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
Other than above
Digital I/O (D)/analog input (A) switching
P25
P24
P23
P22
P21
/ANI5
/ANI4
/ANI3
/AN2
/ANI1
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
A
A
A
D
D
A
A
D
D
D
A
D
D
D
D
D
D
D
D
D
Setting prohibited
P20
/ANI0
A
D
D
D
D
D
D
Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode register 2
(PM2).
2. Do not set the pin set by ADPC0 as digital I/O by ADS, ADDS1, or ADDS0.
3. If data is written to ADPC0, a wait cycle is generated. Do not write data to ADPC0 when the
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 29 CAUTIONS FOR WAIT.
4. If pins ANI0/P20/SEG21 to ANI5/P25/SEG16 are set to segment output via the PF2 register,
output is set to segment output, regardless of the ADPC0 setting.
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User’s Manual U18698EJ1V0UD