UPD78F0411GA-GAM-AX Datasheet, PDF (179/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
Figure 6-30. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Capture Register, CR010: Capture Register) (3/3)
(c) TOC00 = 13H, PRM00 = 00H, CRC00 = 07H, TMC00 = 0AH
TM00 register
0000H
M
O
S
L
N
QR
P
Operable bits ₀₀
10
(TMC003, TMC002)
Capture & count clear input
(TI000 pin input)
Capture register
(CR000)
0000H
L
N
P
R
Capture register
(CR010)
0000H
M
O
Q
Capture interrupt
(INTTM010)
W
T
T
S
W
Capture input ^L
(TI010)
Capture interrupt ^L
(INTTM000)
This is an application example where the pulse width of the signal input to the TI000 pin is measured.
By setting CRC00, the count value can be captured to CR000 in the phase reverse to the falling edge of the
TI000 pin (i.e., rising edge) and to CR010 at the falling edge of the TI000 pin.
The high- and low-level widths of the input pulse can be calculated by the following expressions.
• High-level width = [CR010 value] – [CR000 value] × [Count clock cycle]
• Low-level width = [CR000 value] × [Count clock cycle]
If the reverse phase of the TI000 pin is selected as a trigger to capture the count value to CR000, the INTTM000
signal is not generated. Read the values of CR000 and CR010 to measure the pulse width immediately after the
INTTM010 signal is generated.
However, if the valid edge specified by bits 6 and 5 (ES101 and ES100) of prescaler mode register 00 (PRM00) is
input to the TI010 pin, the count value is not captured but the INTTM000 signal is generated. To measure the
pulse width of the TI000 pin, mask the INTTM000 signal when it is not used.
User’s Manual U18698EJ1V0UD
177