UPD78F0411GA-GAM-AX Datasheet, PDF (194/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-43. Example of Software Processing for PPG Output Operation
TM00 register
M
N
M
N
M
N
0000H
Operable bits
(TMC003, TMC002)
00
11
00
Compare register
(CR000)
M
Compare match interrupt
(INTTM000)
Compare register
N
(CR010)
Compare match interrupt
(INTTM010)
Timer output control bits
(TOE00, TOC004, TOC001)
TO00 output
N+1
M+1
N+1
M+1
N+1
M+1
<1>
<2>
<1> Count operation start flow
<2> Count operation stop flow
START
Register initial setting
PRM00 register,
CRC00 register,
TOC00 register^Note,
CR000, CR010 registers,
port setting
Initial setting of these
registers is performed
before setting the
TMC003 and TMC002
bits.
TMC003, TMC002 bits = 00
The counter is initialized
and counting is stopped
by clearing the TMC003
and TMC002 bits to 00.
STOP
TMC003, TMC002 bits = 11 Starts count operation
Note Care must be exercised when setting TOC00. For details, see 6.3 (3) 16-bit timer output control
register 00 (TOC00).
Remark PPG pulse cycle = (M + 1) × Count clock cycle
PPG duty = (N + 1)/(M + 1)
192
User’s Manual U18698EJ1V0UD