UPD78F0411GA-GAM-AX Datasheet, PDF (438/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 17 INTERRUPT FUNCTIONS
Table 17-1. Interrupt Source List (1/2)
Interrupt Default
Type
Priority^{Note 1}
Name
Interrupt Source
Trigger
Maskable
0
INTLVI
Low-voltage detection^{Note 3}
1
INTP0
Pin input edge detection
2
INTP1
3
INTP2
4
INTP3
5
INTSRE6 UART6 reception error generation
6
INTSR6
End of UART6 reception
7
INTST6
End of UART6 transmission
8
INTST0
End of UART0 transmission
9
INTTMH1 Match between TMH1 and CMP01
(when compare register is specified)
10
INTTMH0 Match between TMH0 and CMP00
(when compare register is specified)
11
INTTM50
Match between TM50 and CR50
(when compare register is specified)
12
INTTM000 Match between TM00 and CR000
(when compare register is specified),
TI010 pin valid edge detection
(when capture register is specified)
13
INTTM010 Match between TM00 and CR010
(when compare register is specified),
TI000 pin valid edge detection
(when capture register is specified)
14
INTAD^{Note 5} End of 10-bit successive approximation type
A/D conversion
15
INTSR0
End of UART0 reception or reception error
generation
16
INTRTC
Fixed-cycle signal of real-time counter/alarm
match detection
17
INTTM51
Match between TM51 and CR51
Note 4
(when compare register is specified)
18
INTKR
Key interrupt detection
19
INTRTCI
Interval signal detection of real-time counter
Internal/
External
Internal
External
Internal
Vector
Table
Address
0004H
0006H
0008H
000AH
000CH
0012H
0014H
0016H
0018H
001AH
Basic
Configuration
Type^{Note 2}
(A)
(B)
(A)
001CH
001EH
0020H
0022H
0024H
0026H
0028H
002AH
External 002CH
(C)
Internal 002EH
(A)
Notes 1.
2.
3.
4.
5.
The default priority determines the sequence of processing vectored interrupts if two or more maskable
interrupts occur simultaneously. Zero indicates the highest priority and 22 indicates the lowest priority.
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 17-1.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
When 8-bit timer/event counter 51 and 8-bit timer H1 are used in the carrier generator mode, an
interrupt is generated upon the timing when the INTTM5H1 signal is generated (see Figure 8-15
Transfer Timing).
μPD78F041x only.
436
User’s Manual U18698EJ1V0UD