UPD78F0411GA-GAM-AX Datasheet, PDF (72/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 3 CPU ARCHITECTURE
3.4.4 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special
function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter
are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. See the [Illustration] shown below.
[Operand format]
Identifier
saddr
saddrp
Description
Immediate data that indicate label or FE20H to FF1FH
Immediate data that indicate label or FE20H to FF1FH (even address only)
[Description example]
MOV 0FE30H, A ; When transferring the value of A register to the saddr (FE30H)
Operation code
11110010
[Illustration]
7
00110000
0
OP code
saddr-offset
OP code
30H (saddr-offset)
15
87
Effective address 1 1 1 1 1 1 1 α
Short direct memory
0
When 8-bit immediate data is 20H to FFH, α = 0
When 8-bit immediate data is 00H to 1FH, α = 1
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User’s Manual U18698EJ1V0UD