UPD78F0411GA-GAM-AX Datasheet, PDF (110/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Figure 5-1. Block Diagram of Clock Generator
Clock operation mode
select register
(OSCCTL)
EXCLK OSCSEL
Main OSC
control register
(MOC)
MSTOP
Main clock
mode register
(MCM)
MCS
STOP
X1/P121
X2/EXCLK/
P122
High-speed system
clock oscillator
fXH
Crystal/ceramic
oscillation
fX
External input
fEXCLK
clock
Internal high-
speed oscillator ^fRH
(8 MHz (TYP.))
XT1/P123
XT2/P124
Subsystem
clock oscillator
Crystal
oscillation
fSUB
fXT
Internal bus
Oscillation stabilization
time select register (OSTS)
OSTS2 OSTS1 OSTS0
3
X1 oscillation
stabilization time counter
Oscillation
stabilization
MOST MOST MOST MOST MOST time counter
11 13 14 15 16 status register
(OSTC)
Controller
Main clock
mode register
(MCM)
XSEL MCM0
Processor clock
control register
(PCC)
CLS CSS PCC2 PCC1 PCC0
4
Peripheral
hardware
clock switch
Peripheral
hardware
clock (fPRS)
Main system fXP
clock switch
Prescaler
fXP fXP fXP fXP
2 2² 2³ 2⁴
fSUB
2
1/2
Internal low-
speed oscillator ^fRL
(240 kHz (TYP.))
CPU clock
(fCPU)
Watchdog timer,
8-bit timer H1,
LCD controller/driver
5
OSCSELS
TTRM4 TTRM3 TTRM2 TTRM1 TTRM0
Clock operation mode
select register
(OSCCTL)
Internal high-speed oscillation
trimming register (HIOTRM)
Internal bus
RSTS LSRSTOP RSTOP
Internal oscillation
mode register
(RCM)
Option byte
1: Cannot be stopped
0: Can be stopped