UPD78F0411GA-GAM-AX Datasheet, PDF (139/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATOR
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (3/4)
(6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(C) → (B)
RSTOP
0
RSTS
Confirm this flag is 1.
MCM0
0
Unnecessary if the CPU is operating
with the internal high-speed oscillation clock
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(C) → (D)
OSCSELS
1
Waiting for Oscillation
Stabilization
Necessary
CSS
1
Unnecessary if the CPU is operating
with the subsystem clock
(8) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(D) → (B)
RSTOP
0
RSTS
Confirm this flag
is 1.
Unnecessary if the CPU is operating
with the internal high-speed
oscillation clock
MCM0
0
↑
Unnecessary if
XSEL is 0
CSS
0
Remarks 1. (A) to (I) in Table 5-5 correspond to (A) to (I) in Figure 5-15.
2. MCM0:
Bit 0 of the main clock mode register (MCM)
OSCSELS:
Bit 4 of the clock operation mode select register (OSCCTL)
RSTS, RSTOP:
Bits 7 and 0 of the internal oscillation mode register (RCM)
CSS:
Bit 4 of the processor clock control register (PCC)
User’s Manual U18698EJ1V0UD
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