UPD78F0411GA-GAM-AX Datasheet, PDF (177/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
(4) Operation in clear & start mode entered by TI000 pin valid edge input
(CR000: capture register, CR010: capture register)
Figure 6-29. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Capture Register, CR010: Capture Register)
Operable bits
TMC003, TMC002
Count clock
Clear
Timer counter
(TM00)
TI000 pin
TI010 pin^Note
Edge
detection
Edge
detection
Capture signal
Capture register
(CR010)
Capture
signal
Capture register
(CR000)
Output
controller
Interrupt signal
(INTTM010)
TO00
output
TO00 pin^Note
Interrupt signal
(INTTM000)
Note The timer output (TO00) cannot be used when detecting the valid edge of the TI010 pin is used.
Figure 6-30. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Capture Register, CR010: Capture Register) (1/3)
(a) TOC00 = 13H, PRM00 = 30H, CRC00 = 05H, TMC00 = 0AH
TM00 register
0000H
Operable bits
(TMC003, TMC002)
00
Capture & count clear input
(TI000 pin input)
Capture register
(CR000)
Capture interrupt
(INTTM000) ^L
Capture register
(CR010)
Capture interrupt
(INTTM010)
L
M
10
N
OP
Q
RS
0000H
0000H
L M NO P Q R
T
ST
TO00 output
This is an application example where the count value is captured to CR010, TM00 is cleared, and the TO00
output is inverted when the rising or falling edge of the TI000 pin is detected.
When the edge of the TI010 pin is detected, an interrupt signal (INTTM000) is generated. Mask the INTTM000
signal when it is not used.
User’s Manual U18698EJ1V0UD
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