UPD78F0411GA-GAM-AX Datasheet, PDF (149/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
(iii) Setting range when CR000 or CR010 is used as a compare register
When CR000 or CR010 is used as a compare register, set it as shown below.
Operation
Operation as interval timer
Operation as square-wave output
Operation as external event counter
Operation in the clear & start mode
entered by TI000 pin valid edge input
Operation as free-running timer
Operation as PPG output
Operation as one-shot pulse output
CR000 Register Setting Range
0000H < N ≤ FFFFH
0000H^Note ≤ N ≤ FFFFH
CR010 Register Setting Range
0000H^Note ≤ M ≤ FFFFH
Normally, this setting is not used. Mask the
match interrupt signal (INTTM010).
0000H^Note ≤ M ≤ FFFFH
M < N ≤ FFFFH
0000H^Note ≤ N ≤ FFFFH (N ≠ M)
0000H^Note ≤ M < N
0000H^Note ≤ M ≤ FFFFH (M ≠ N)
Note When 0000H is set, a match interrupt immediately after the timer operation does not occur and timer output
is not changed, and the first match timing is as follows. A match interrupt occurs at the timing when the
timer counter (TM00 register) is changed from 0000H to 0001H.
• When the timer counter is cleared due to overflow
• When the timer counter is cleared due to TI000 pin valid edge (when clear & start mode is entered by
TI000 pin valid edge input)
• When the timer counter is cleared due to compare match (when clear & start mode is entered by match
between TM00 and CR000 (CR000 = other than 0000H, CR010 = 0000H))
Timer counter clear
TM00 register
Compare register set value
(0000H)
Timer operation enable bit
Operation
disabled (00)
(TMC003, TMC002)
Operation enabled
(other than 00)
Interrupt request signal
Interrupt signal
is not generated
Interrupt signal
is generated
Remarks 1. N: CR000 register set value, M: CR010 register set value
2. For details of TMC003 and TMC002, see 6.3 (1) 16-bit timer mode control register 00 (TMC00).
User’s Manual U18698EJ1V0UD
147