UPD78F0411GA-GAM-AX Datasheet, PDF (532/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 26 INSTRUCTION SET
26.2 Operation List
Instruction
Mnemonic
Group
Operands
Bytes
Clocks
Note 1 Note 2
Operation
8-bit data
transfer
MOV
r, #byte
saddr, #byte
2
4
3
6
− r ← byte
7 (saddr) ← byte
sfr, #byte
A, r
r, A
3
−
Note 3
1
2
Note 3
1
2
7 sfr ← byte
− A←r
− r←A
A, saddr
2
4
5 A ← (saddr)
saddr, A
2
4
5 (saddr) ← A
A, sfr
2
−
5 A ← sfr
sfr, A
2
−
5 sfr ← A
A, !addr16
3
8
9 A ← (addr16)
!addr16, A
3
8
9 (addr16) ← A
PSW, #byte
3
−
7 PSW ← byte
A, PSW
2
−
5 A ← PSW
PSW, A
2
−
5 PSW ← A
A, [DE]
1
4
5 A ← (DE)
[DE], A
1
4
5 (DE) ← A
A, [HL]
1
4
5 A ← (HL)
[HL], A
1
4
5 (HL) ← A
A, [HL + byte]
2
8
9 A ← (HL + byte)
[HL + byte], A
2
8
9 (HL + byte) ← A
A, [HL + B]
1
6
7 A ← (HL + B)
[HL + B], A
1
6
7 (HL + B) ← A
A, [HL + C]
1
6
7 A ← (HL + C)
XCH
[HL + C], A
A, r
1
6
Note 3
1
2
7 (HL + C) ← A
− A↔r
A, saddr
2
4
6 A ↔ (saddr)
A, sfr
2
−
6 A ↔ (sfr)
A, !addr16
3
8
10 A ↔ (addr16)
A, [DE]
1
4
6 A ↔ (DE)
A, [HL]
1
4
6 A ↔ (HL)
A, [HL + byte]
2
8
10 A ↔ (HL + byte)
A, [HL + B]
2
8
10 A ↔ (HL + B)
A, [HL + C]
2
8
10 A ↔ (HL + C)
Flag
Z AC CY
×××
×××
Notes 1.
2.
3.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
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User’s Manual U18698EJ1V0UD