UPD78F0411GA-GAM-AX Datasheet, PDF (217/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
(4) Timing of holding data by capture register
(a) When the valid edge is input to the TI000/TI010 pin and the reverse phase of the TI000 pin is detected while
CR000/CR010 is read, CR010 performs a capture operation but the read value of CR000/CR010 is not
guaranteed. At this time, an interrupt signal (INTTM000/INTTM010) is generated when the valid edge of the
TI000/TI010 pin is detected (the interrupt signal is not generated when the reverse-phase edge of the TI000
pin is detected).
When the count value is captured because the valid edge of the TI000/TI010 pin was detected, read the
value of CR000/CR010 after INTTM000/INTTM010 is generated.
Figure 6-60. Timing of Holding Data by Capture Register
Count pulse
TM00 count value
Edge input
INTTM010
Capture read signal
Value captured to CR010
N
N+1 N+2
X
Capture operation
M
M+1 M+2
N+1
Capture operation is performed
but read value is not guaranteed.
(b) The values of CR000 and CR010 are not guaranteed after 16-bit timer/event counter 00 stops.
(5) Setting valid edge
Set the valid edge of the TI000 pin while the timer operation is stopped (TMC003 and TMC002 = 00). Set the
valid edge by using ES000 and ES001.
(6) Re-triggering one-shot pulse
Make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode.
Be sure to input the next trigger after the current active level is output.
User’s Manual U18698EJ1V0UD
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