UPD78F0411GA-GAM-AX Datasheet, PDF (242/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 8 8-BIT TIMERS H0, H1, AND H2
Figure 8-6. Format of 8-Bit Timer H Mode Register 0 (TMHMD0)
Address: FF69H After reset: 00H R/W
TMHMD0
<7>
6
5
4
3
2
<1>
<0>
TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0
TMHE0
Timer operation enable
0 Stops timer count operation (counter is cleared to 0)
1 Enables timer count operation (count operation started by inputting clock)
CKS02 CKS01 CKS00
Count clock selection^{Note 1}
fPRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
0
0
0
f ^{Note 2}
PRS
2 MHz 5 MHz 10 MHz
0
0
1
fPRS/2
1 MHz 2.5 MHz 5 MHz
0
1
0
fPRS/2²
500 kHz 1.25 MHz 2.5 MHz
0
1
1
fPRS/2⁶
31.25 kHz 78.13 kHz 156.25 kHz
1
0
0
1
0
1
Other than above
fPRS/2¹⁰
1.95 kHz 4.88 kHz 9.77 kHz
TM50 output^{Note 3}
Setting prohibited
TMMD01 TMMD00
Timer operation mode
0
0 Interval timer mode
1
0 Input enable width adjust mode for pins (PWM mode)
Other than above Setting prohibited
TOLEV0
0 Low level
1 High level
Timer output level control (in default mode)
TOEN0
0 Disables output
1 Enables output
Timer output control
Notes 1.
2.
3.
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
• VDD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• VDD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V ≤ VDD < 2.7 V, the setting of CKS02 = CKS01 = CKS00 = 0 (count clock: fPRS) is
prohibited.
When selecting the TM50 output as the count clock, start the operation of the 8-bit timer/event counter
50 first and then enable the timer F/F inversion operation (TMC501 = 1).
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User’s Manual U18698EJ1V0UD