UPD78F0411GA-GAM-AX Datasheet, PDF (375/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 14 SERIAL INTERFACE UART6
(4) Permissible baud rate range during reception
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
using the calculation expression shown below.
Figure 14-27. Permissible Baud Rate Range During Reception
Latch timing
Data frame length
of UART6
Start bit
Bit 0
FL
Bit 1
Bit 7 Parity bit Stop bit
1 data frame (11 × FL)
Minimum permissible
data frame length
Start bit Bit 0
Bit 1
Bit 7 Parity bit Stop bit
FLmin
Maximum permissible
data frame length
Start bit
Bit 0
Bit 1
Bit 7 Parity bit Stop bit
FLmax
As shown in Figure 14-27, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
FL = (Brate)^−1
Brate: Baud rate of UART6
k: Set value of BRGC6
FL: 1-bit data length
Margin of latch timing: 2 clocks
User’s Manual U18698EJ1V0UD
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