UPD78F0411GA-GAM-AX Datasheet, PDF (68/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 3 CPU ARCHITECTURE
3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the
immediate data of an operation code are transferred to the program counter (PC) and branched.
This function is carried out when the CALLT [addr5] instruction is executed.
This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to
the entire memory space.
[Illustration]
7 65
Operation code 1 1
ta4–0
10
1
15
8 7 65
Effective address 0 0 0 0 0 0 0 0 0 1
10
0
7
Memory (Table)
0
Low Addr.
Effective address+1
High Addr.
15
87
0
PC
3.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
07
0
rp
A
X
15
87
0
PC
66
User’s Manual U18698EJ1V0UD