UPD78F0411GA-GAM-AX Datasheet, PDF (113/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATOR
(2) Processor clock control register (PCC)
This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock.
PCC is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PCC to 01H.
Figure 5-3. Format of Processor Clock Control Register (PCC)
Address: FFFBH After reset: 01H
Symbol
7
6
PCC
0
0
R/W^Note
<5>
CLS
<4>
CSS
3
2
1
0
PCC2
PCC1
0
PCC0
CLS
0
Main system clock
1
Subsystem clock
CPU clock status
CSS
0
1
PCC2
PCC1
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
0
1
1
0
Other than above
Note Bit 5 is read-only.
PCC0
0
1
0
1
0
0
1
0
1
0
CPU clock (fCPU) selection
fXP
fXP/2 (default)
fXP/2²
fXP/2³
fXP/2⁴
fSUB/2
Setting prohibited
Caution Be sure to clear bits 3, 6, and 7 to “0”.
Remarks 1. fXP: Main system clock oscillation frequency
2. fSUB: Subsystem clock oscillation frequency
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/LC3. Therefore, the relationship
between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 5-2.
User’s Manual U18698EJ1V0UD
111