UPD78F0411GA-GAM-AX Datasheet, PDF (387/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 15 LCD CONTROLLER/DRIVER
15.4 Setting LCD Controller/Driver
Set the LCD controller/driver using the following procedure.
<1> Set (VAON = 1) internal gate voltage boosting (bit 4 of the LCD display mode register (LCDM))
<2> Set the resistance division method via MDSET0 and MDSET1 (bits 4 and 5 of the LCD mode register
(LCDMD)) (MDSET0 = 0: external resistance division method, MDSET0 = 1: internal resistance
division method).
<3> Set the pins to be used as segment outputs to the port function registers (PF2m, PFnALL).
<4> Set LCD display RAM to the initial value.
<5> Set the number of time slices via LCDM0 to LCDM2 (bits 0 to 2 of the LCD display mode register
(LCDM)).
<6> Set the LCD source clock and LCD clock via LCD clock control register 0 (LCDC0).
<7> Set (SCOC = 1) SCOC (bit 6 of the LCD display mode register (LCDM)).
Non-selected waveforms are output from all the segment and common pins, and the non-display status
is entered.
<8> Start output corresponding to each data memory by setting (LCDON = 1) LCDON (bit 7 of LCDM).
Subsequent to this procedure, set the data to be displayed in the data memory.
Note Set VAON based on the following conditions.
<When set to the static display mode>
• When 2.0 V ≤ VLCD ≤ VDD ≤ 5.5 V: VAON = 0
• When 1.8 V ≤ VLCD ≤ VDD ≤ 3.6 V: VAON = 1
<When set to the 1/3 bias method>
• When 2.5 V ≤ VLCD ≤ VDD ≤ 5.5 V: VAON = 0
• When 1.8 V ≤ VLCD ≤ VDD ≤ 3.6 V: VAON = 1
<When set to the 1/2 bias method>
• When 2.7 V ≤ VLCD ≤ VDD ≤ 5.5 V: VAON = 0
• When 1.8 V ≤ VLCD ≤ VDD ≤ 3.6 V: VAON = 1
<When set to the 1/4 bias method>
• When 4.5 V ≤ VLCD ≤ VDD ≤ 5.5 V: VAON = 0
Remark m = 0 to 5, n = 10, 11, 14 or 15
User’s Manual U18698EJ1V0UD
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