UPD78F0411GA-GAM-AX Datasheet, PDF (227/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52
(2) 8-bit timer mode control register 5n (TMC5n)
TMC5n is a register that controls the count operation of 8-bit timer counter 5n (TM5n).
TMC5n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Remark n = 0 to 2
Figure 7-9. Format of 8-Bit Timer Mode Control Register 50 (TMC50)
Address: FF6BH After reset: 00H R/W^Note
Symbol
<7>
6
5
TMC50
TCE50
0
0
4
<3>
<2>
1
0
0
LVS50
LVR50
TMC501
0
TCE50
0
1
TM50 count operation control
After clearing to 0, count operation disabled (counter stopped)
Count operation start
LVS50
0
0
1
1
LVR50
0
1
0
1
Timer output F/F status setting
No change
Timer output F/F clear (0) (default value of TM50 output: low level)
Timer output F/F set (1) (default value of TM50 output: high level)
Setting prohibited
TMC501
0
1
Inversion operation disabled
Inversion operation enabled
Timer F/F control
Note Bits 2 and 3 are write-only.
Cautions 1. Be sure to clear bits 0, and 4 to 6 to 0.
2. Perform <1> to <3> below in the following order, not at the same time.
<1> Set TMC501:
Operation mode setting
<2> Set LVS50, LVR50:
Timer F/F setting
<4> Set TCE50
Remark If LVS50 and LVR50 are read, the value is 0.
User’s Manual U18698EJ1V0UD
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