UPD78F0411GA-GAM-AX Datasheet, PDF (142/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATOR
5.6.8 Time required for switchover of CPU clock and main system clock
By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock
can be switched (between the main system clock and the subsystem clock) and the division ratio of the main system
clock can be changed.
The actual switchover operation is not performed immediately after rewriting to PCC; operation continues on the
pre-switchover clock for several clocks (see Table 5-7).
Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 5
(CLS) of the PCC register.
Table 5-7. Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor
Set Value Before
Switchover
Set Value After Switchover
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
000000010010001101001×××
0000
16 clocks
16 clocks
16 clocks
16 clocks
2fXP/fSUB clocks
001
8 clocks
8 clocks
8 clocks
8 clocks
fXP/fSUB clocks
010
4 clocks
4 clocks
4 clocks
4 clocks
fXP/2fSUB clocks
011
2 clocks
2 clocks
2 clocks
2 clocks
fXP/4fSUB clocks
100
1 clock
1 clock
1 clock
1 clock
fXP/8fSUB clocks
1×××
2 clocks
2 clocks
2 clocks
2 clocks
2 clocks
Caution Selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the
main system clock to the subsystem clock (changing CSS from 0 to 1) should not be set
simultaneously.
Simultaneous setting is possible, however, for selection of the main system clock cycle division
factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock
(changing CSS from 1 to 0).
Remarks 1. The number of clocks listed in Table 5-7 is the number of CPU clocks before switchover.
2. When switching the CPU clock from the main system clock to the subsystem clock, calculate the
number of clocks by rounding up to the next clock and discarding the decimal portion, as shown
below.
Example When switching CPU clock from fXP/2 to fSUB/2 (@ oscillation with fXP = 10 MHz, fSUB =
32.768 kHz)
fXP/fSUB = 10000/32.768 ≅ 305.1 → 306 clocks
By setting bit 0 (MCM0) of the main clock mode register (MCM), the main system clock can be switched (between
the internal high-speed oscillation clock and the high-speed system clock).
The actual switchover operation is not performed immediately after rewriting to MCM0; operation continues on the
pre-switchover clock for several clocks (see Table 5-8).
Whether the CPU is operating on the internal high-speed oscillation clock or the high-speed system clock can be
ascertained using bit 1 (MCS) of MCM.
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User’s Manual U18698EJ1V0UD