UPD78F0411GA-GAM-AX Datasheet, PDF (136/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATOR
5.6.6 CPU clock status transition diagram
Figure 5-15 shows the CPU clock status transition diagram of this product.
Figure 5-15. CPU Clock Status Transition Diagram
(When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
Power ON
(A) _{Reset release}
Internal low-speed oscillation: Woken up
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (I/O port mode)
XT1 oscillation input: Stops (Input port mode)
VDD < 1.59 V (TYP.)
VDD ≥ 1.59 V (TYP.)
Internal low-speed oscillation: Operating
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (I/O port mode)
XT1 oscillation input: Stops (Input port mode)
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation input: Operating
(B) ^{Internal low-speed oscillation: Operable}
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
(D) Selectable by CPU
XT1 oscillation input: Selectable by CPU
CPU: Operating
with internal high-
speed oscillation
CPU: Operating
with XT1 oscillation
input
VDD ≥ 1.8 V (MIN.)
(H)
CPU: Internal high-
speed oscillation
→ STOP
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation input: Operable
(E)
(G)
(C)
CPU: XT1
oscillation input
→ HALT
CPU: Operating
with X1 oscillation or
EXCLK input
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operable
X1 oscillation/EXCLK input: Operable
XT1 oscillation input: Operating
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input: Operating
XT1 oscillation input: Selectable by CPU
(F)
CPU: X1
oscillation/EXCLK
input → HALT
CPU: Internal high-
speed oscillation
→ HALT
(I)
CPU: X1
oscillation/EXCLK
input → STOP
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operable
X1 oscillation/EXCLK input: Operating
XT1 oscillation input: Operable
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input: Operable
XT1 oscillation input: Operable
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation: Operable
Remark In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the CPU clock status changes to (A) in the
above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (11 to 47
μs (TYP.)).
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User’s Manual U18698EJ1V0UD