UPD78F0411GA-GAM-AX Datasheet, PDF (463/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 19 STANDBY FUNCTION
Table 19-1. Operating Statuses in HALT Mode (2/2)
HALT Mode Setting
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
Item
When CPU Is Operating on XT1 Clock (fXT)
System clock
Clock supply to the CPU is stopped
Main system clock fRH
Status before HALT mode was set is retained
fX
fEXCLK Operates or stops by external clock input
Subsystem clock fXT
Operation continues (cannot be stopped)
fRL
Status before HALT mode was set is retained
CPU
Operation stopped
Flash memory
RAM
Status before HALT mode was set is retained
Port (latch)
16-bit timer/event counter 00^Note1 Operable
8-bit timer/event
counter
50
51
52^{Note 1}
8-bit timer
H0
H1
H2
Real-time counter
Watchdog timer
Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Buzzer output
Operable. However, operation disabled when peripheral hardware clock (fPRS) is stopped.
10-bit successive approximation
type A/D converter^{Note 2}
Serial interface UART0
Operable
UART6
LCD controller/driver
Manchester code generator
Power-on-clear function
Low-voltage detection function
External interrupt
Notes 1. When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been
stopped, do not start operation of these functions on the external clock input from peripheral hardware pins.
2. μPD78F041x only.
Remark
fRH:
fX:
fEXCLK:
fXT:
fRL:
Internal high-speed oscillation clock
X1 clock
External main system clock
XT1 clock
Internal low-speed oscillation clock
User’s Manual U18698EJ1V0UD
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