UPD78F0411GA-GAM-AX Datasheet, PDF (69/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 3 CPU ARCHITECTURE
3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
3.4.1 Implied addressing
[Function]
The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically
(implicitly) addressed.
Of the 78K0/LC3 instruction words, the following instructions employ implied addressing.
Instruction
MULU
DIVUW
ADJBA/ADJBS
ROR4/ROL4
Register to Be Specified by Implied Addressing
A register for multiplicand and AX register for product storage
AX register for dividend and quotient storage
A register for storage of numeric values that become decimal correction targets
A register for storage of digit data that undergoes digit rotation
[Operand format]
Because implied addressing can be automatically determined with an instruction, no particular operand format is
necessary.
[Description example]
In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of the A register and X register is stored in AX. In this
example, the A and AX registers are specified by implied addressing.
User’s Manual U18698EJ1V0UD
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