UPD78F0411GA-GAM-AX Datasheet, PDF (301/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only)
(4) Analog input channel specification register (ADS)
This register specifies the input channel of the analog voltage to be A/D converted.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 12-8. Format of Analog Input Channel Specification Register (ADS)
Address: FF8EH After reset: 00H R/W
Symbol 7
6
5
4
ADS 0
0
0
0
3
2
1
0
0
ADS2 ADS1 ADS0
ADS2
0
0
0
0
1
1
1
1
ADS1
0
0
1
1
0
0
1
1
ADS0
0
1
0
1
0
1
0
1
Analog input channel specification
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
Setting prohibited
Cautions 1. Be sure to clear bits 3 to 7 to “0”.
2. Set a channel to be used for A/D conversion in the input mode by using port mode register 2
(PM2).
3. Do not set a pin to be used as a digital I/O pin with ADPC with ADS.
4. If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the CPU is
operating on the subsystem clock and the peripheral hardware clock is stopped. For details,
see CHAPTER 29 CAUTIONS FOR WAIT.
(5) A/D port configuration register 0 (ADPC0)
This register switches the ANI0/P20 to ANI5/P25 pins to analog input (analog input of 16-bit ΔΣ type A/D
converter or analog input of 10-bit successive approximation type A/D converter) or digital I/O of port.
ADPC0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 08H.
User’s Manual U18698EJ1V0UD
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