UPD78F0411GA-GAM-AX Datasheet, PDF (291/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 11 BUZZER OUTPUT CONTROLLER
Figure 11-2. Format of Clock Output Selection Register (CKS)
Address: FF40H After reset: 00H R/W
Symbol
<7>
6
5
4
3
2
1
0
CKS
BZOE
BCS1
BCS0
0
0
0
0
0
BZOE
0
1
BUZ output enable/disable specification
Clock division circuit operation stopped. BUZ fixed to low level.
Clock division circuit operation enabled. BUZ output enabled.
BCS1
0
0
1
1
BCS0
0
fPRS/2¹⁰
1
fPRS/2¹¹
0
fPRS/2¹²
1
fPRS/2¹³
BUZ output clock selection
fPRS = 5 MHz
fPRS = 10 MHz
4.88 kHz
9.77 kHz
2.44 kHz
4.88 kHz
1.22 kHz
2.44 kHz
0.61 kHz
1.22 kHz
Caution Set BCS1 and BCS0 when the buzzer output operation is stopped (BZOE = 0).
Remark fPRS: Peripheral hardware clock frequency
User’s Manual U18698EJ1V0UD
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