UPD78F0411GA-GAM-AX Datasheet, PDF (507/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 23 OPTION BYTE
23.2 Format of Option Byte
The format of the option byte is shown below.
Figure 23-1. Format of Option Byte (1/2)
Address: 0080H/1080H^Note
7
6
0
WINDOW1
5
WINDOW0
4
WDTON
3
WDCS2
2
WDCS1
1
WDCS0
0
LSROSC
WINDOW1
0
0
1
1
WINDOW0
0
1
0
1
25%
50%
75%
100%
Watchdog timer window open period
WDTON
0
1
Operation control of watchdog timer counter/illegal access detection
Counter operation disabled (counting stopped after reset), illegal access detection operation
disabled
Counter operation enabled (counting started after reset), illegal access detection operation enabled
WDCS2
0
0
0
0
1
1
1
1
WDCS1
0
0
1
1
0
0
1
1
WDCS0
0
1
0
1
0
1
0
1
Watchdog timer overflow time
2¹⁰/fRL (3.88 ms)
2¹¹/fRL (7.76 ms)
2¹²/fRL (15.52 ms)
2¹³/fRL (31.03 ms)
2¹⁴/fRL (62.06 ms)
2¹⁵/fRL (124.12 ms)
2¹⁶/fRL (248.24 ms)
2¹⁷/fRL (496.48 ms)
LSROSC
0
1
Internal low-speed oscillator operation
Can be stopped by software (stopped when 1 is written to bit 1 (LSRSTOP) of RCM register)
Cannot be stopped (not stopped even if 1 is written to LSRSTOP bit)
Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the
boot swap operation.
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is
prohibited.
2. The watchdog timer continues its operation during self-programming and EEPROM emulation of
the flash memory. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
3. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the
watchdog timer in the HALT and STOP modes, regardless of the setting of bit 1 (LSRSTOP) of
the internal oscillation mode register (RCM).
When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is
supplied to 8-bit timer H1 even in the HALT/STOP mode.
4. Be sure to clear bit 7 to 0.
Remarks 1. fRL: Internal low-speed oscillation clock frequency
2. ( ): fRL = 264 kHz (MAX.)
User’s Manual U18698EJ1V0UD
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