UPD78F0411GA-GAM-AX Datasheet, PDF (499/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 22 LOW-VOLTAGE DETECTOR
Figure 22-7. Timing of Low-Voltage Detector Interrupt Signal Generation
(Detects Level of Supply Voltage (VDD)) (2/2)
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
Supply voltage (VDD)
VLVI
2.7 V(TYP.)
VPOC = 1.59 V (TYP.)
Note 3
Note 3
LVIMK flag
(set by software)
LVISEL flag
(set by software) _L
<1>
Note 1
<8> Cleared by software
<3>
LVION flag
(set by software)
LVIF flag
INTLVI
<2>
<4>
<5> Wait time
<6>
Note 2
LVIIF flag
LVIMD flag
(set by software) _L
Internal reset signal
Note 2
<7>
Note 2 Cleared by software
<9>
Time
Notes 1.
2.
3.
The LVIMK flag is set to “1” by reset signal generation.
The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
If LVION is cleared (0) in a state below the LVI detection voltage, an INTLVI signal is generated and
LVIIF becomes 1.
Remark <1> to <9> in Figure 22-7 above correspond to <1> to <9> in the description of “When starting
operation” in 22.4.2 (1) When detecting level of supply voltage (VDD).
User’s Manual U18698EJ1V0UD
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