UPD78F0411GA-GAM-AX Datasheet, PDF (465/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 19 STANDBY FUNCTION
(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 19-4. HALT Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
HALT
instruction
Reset signal
Status of CPU
High-speed
system clock
(X1 oscillation)
Normal operation
(high-speed
system clock)
HALT mode
Oscillates
Reset
Reset ^processing
period ^{(11 to 47 μs)}
Oscillation Oscillation
stopped stopped
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Oscillation stabilization time
Starting X1 oscillation is ^{(211/fX to 216/fX)}
specified by software.
(2) When internal high-speed oscillation clock is used as CPU clock
HALT
instruction
Reset signal
Normal operation
(internal high-speed
Status of CPU oscillation clock)
HALT mode
Internal high-speed
oscillation clock
Oscillates
Reset
Reset processing
period (11 to 47 μs)
Oscillation
stopped
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Wait for oscillation
accuracy stabilization
(86 to 361 μs)
(3) When subsystem clock is used as CPU clock
HALT
instruction
Reset signal
Normal operation
Status of CPU (subsystem clock)
HALT mode
Subsystem clock
(XT1 oscillation)
Oscillates
Reset _{Normal operation mode}
Reset ^processing (internal high-speed
period (11 to 47 μs)
oscillation clock)
Oscillation Oscillation
stopped stopped Oscillates
Remark fX: X1 clock oscillation frequency
Starting XT1 oscillation is
specified by software.
User’s Manual U18698EJ1V0UD
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