UPD78F0411GA-GAM-AX Datasheet, PDF (137/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATOR
Table 5-5 shows transition of the CPU clock and examples of setting the SFR registers.
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (1/4)
(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
(A) → (B)
Status Transition
SFR Register Setting
SFR registers do not have to be set (default status after reset release).
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Status Transition
Setting Flag of SFR Register
EXCLK
OSCSEL MSTOP OSTC
Register
XSEL
MCM0
(A) → (B) → (C) (X1 clock)
0
1
0
Must be
1
1
checked
(A) → (B) → (C) (external main clock)
1
1
0
Must not be
1
1
checked
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)).
(3) CPU operating with subsystem clock (D) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(A) → (B) → (D)
OSCSELS
1
Waiting for Oscillation
Stabilization
Necessary
CSS
1
Remarks 1. (A) to (I) in Table 5-5 correspond to (A) to (I) in Figure 5-15.
2. EXCLK, OSCSEL, OSCSELS:
Bits 7, 6, and 4 of the clock operation mode select register (OSCCTL)
MSTOP:
Bit 7 of the main OSC control register (MOC)
XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM)
CSS:
Bit 4 of the processor clock control register (PCC)
User’s Manual U18698EJ1V0UD
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