UPD78F0411GA-GAM-AX Datasheet, PDF (345/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 14 SERIAL INTERFACE UART6
Figure 14-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)
PS61
0
0
1
1
PS60
0
1
0
1
Transmission operation
Does not output parity bit.
Outputs 0 parity.
Outputs odd parity.
Outputs even parity.
Reception operation
Reception without parity
Reception as 0 parity^Note
Judges as odd parity.
Judges as even parity.
CL6
Specifies character length of transmit/receive data
0
Character length of data = 7 bits
1
Character length of data = 8 bits
SL6
Specifies number of stop bits of transmit data
0
Number of stop bits = 1
1
Number of stop bits = 2
ISRM6
0
1
Enables/disables occurrence of reception completion interrupt in case of error
“INTSRE6” occurs in case of error (at this time, INTSR6 does not occur).
“INTSR6” occurs in case of error (at this time, INTSRE6 does not occur).
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial
interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur.
Cautions 1. To start the transmission, set POWER6 to 1 and then set TXE6 to 1. To stop the transmission,
clear TXE6 to 0, and then clear POWER6 to 0.
2. To start the reception, set POWER6 to 1 and then set RXE6 to 1. To stop the reception, clear
RXE6 to 0, and then clear POWER6 to 0.
3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RXD6 pin. If
POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started.
4. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To enable
transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock
after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the
base clock, the transmission circuit or reception circuit may not be initialized.
5. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1.
6. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.
7. Fix the PS61 and PS60 bits to 0 when used in LIN communication operation.
8. Clear TXE6 to 0 before rewriting the SL6 bit. Reception is always performed with “the
number of stop bits = 1”, and therefore, is not affected by the set value of the SL6 bit.
9. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
User’s Manual U18698EJ1V0UD
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