UPD78F0411GA-GAM-AX Datasheet, PDF (138/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATOR
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (2/4)
(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(B) → (C) (X1 clock)
EXCLK
0
(B) → (C) (external main clock)
1
OSCSEL
1
1
MSTOP
0
0
OSTC
Register
Must be
checked
Must not be
checked
XSEL^Note
1
1
MCM0
1
1
Unnecessary if these Unnecessary if the CPU
registers are already set is operating with the
high-speed system clock
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
already been set.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)).
(5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(B) → (D)
OSCSELS
1
Waiting for Oscillation
Stabilization
Necessary
CSS
1
Remarks 1. (A) to (I) in Table 5-5 correspond to (A) to (I) in Figure 5-15.
2. EXCLK, OSCSEL, OSCSELS:
Bits 7, 6, and 4 of the clock operation mode select register (OSCCTL)
MSTOP:
Bit 7 of the main OSC control register (MOC)
XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM)
CSS:
Bit 4 of the processor clock control register (PCC)
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User’s Manual U18698EJ1V0UD