UPD78F0411GA-GAM-AX Datasheet, PDF (183/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
6.4.5 Free-running timer operation
When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 01 (free-
running timer mode), 16-bit timer/event counter 00 continues counting up in synchronization with the count clock.
When it has counted up to FFFFH, the overflow flag (OVF00) is set to 1 at the next clock, and TM00 is cleared (to
0000H) and continues counting. Clear OVF00 to 0 by executing the CLR instruction via software.
The following three types of free-running timer operations are available.
• Both CR000 and CR010 are used as compare registers.
• One of CR000 or CR010 is used as a compare register and the other is used as a capture register.
• Both CR000 and CR010 are used as capture registers.
Remarks 1. For the setting of the I/O pins, see 6.3 (6) Port mode register 3 (PM3).
2. For how to enable the INTTM000 signal interrupt, see CHAPTER 17 INTERRUPT FUNCTIONS.
(1) Free-running timer mode operation
(CR000: compare register, CR010: compare register)
Figure 6-33. Block Diagram of Free-Running Timer Mode
(CR000: Compare Register, CR010: Compare Register)
Count clock
Operable bits
TMC003, TMC002
Timer counter
(TM00)
Match signal
Compare register
(CR000)
Match signal
Output
controller
Interrupt signal
(INTTM000)
TO00
output
TO00 pin
Interrupt signal
(INTTM010)
Compare register
(CR010)
User’s Manual U18698EJ1V0UD
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