UPD78F0411GA-GAM-AX Datasheet, PDF (420/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 16 MANCHESTER CODE GENERATOR
(b) MCG control register 1 (MC0CTL1)
This register is used to set the base clock of the Manchester code generator.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: FF4DH After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
MC0CTL1
0
0
0
0
0
MC0CKS2 MC0CKS1 MC0CKS0
MC0CKS2
0
0
0
0
1
1
1
1
MC0CKS1
0
0
1
1
0
0
1
1
MC0CKS0
0
1
0
1
0
1
0
1
Base clock (fXCLK) selection^{Note 1}
fPRS^{Note 2} (10 MHz)
fPRS/2 (5 MHz)
fPRS/2² (2.5 MHz)
fPRS/2³ (1.25 MHz)
fPRS/2⁴ (625 kHz)
fPRS/2⁵ (312.5 kHz)
Setting prohibited
Notes 1.
2.
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL =
1), the fPRS operating frequency varies depending on the supply voltage.
• VDD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• VDD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock
(fRH) (XSEL = 0), when 1.8 V ≤ VDD < 2.7 V, the setting of MC0CKS2 = MC0CKS1 =
MC0CKS0 = 0 (base clock: fPRS) is prohibited.
Caution Clear bit 7 (MC0PWR) of the MC0CTL0 register to 0 before rewriting the MC0CKS2 to
MC0CKS0 bits.
Remarks 1. fPRS: Peripheral hardware clock frequency
2. Figures in parentheses are for operation with fPRS = 10 MHz.
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User’s Manual U18698EJ1V0UD